Automatización y mejora de la etapa de síntesis lógica, optimización del proceso de instalación de aplicaciones de Synopsys y simulación para el diseño del circuito integrado "El Gran Jaguar" en su adaptación a la tecnología de 65 nm

Abstract

El presente trabajo de tesis se enfoca en la automatización y mejora de la etapa de síntesis lógica, la optimización del proceso de instalación de aplicaciones de Synopsys y la simulación para el diseño del circuito integrado "El Gran Jaguar" en su adaptación a la tecnología de 65 nm. Se detallan los flujos de diseño, herramientas y metodologías empleadas para lograr estos objetivos, incluyendo la síntesis de diversos circuitos digitales y la verificación experimental mediante FPGA.

In this thesis, an improved methodology for the logic synthesis and experimental verification of the nanochip "El Gran Jaguar" is presented, aligned with the design flow recommended by Synopsys. As part of the methodological process, five preliminary circuits were synthesized in order to validate the proposed ow before addressing the complete design of the nanochip. All syntheses were carried out using TSMC's 65 nm technology, yielding correct results in the simulations. In particular, the ring oscillator exhibited proper behavior, overcoming inconsistencies reported in previous work. Subsequently, the nanochip's core was implemented on a Xilinx Virtex-5 Genesys FPGA to perform its verification through a FPGA prototyping approach. In this scheme, the FPGA serves as a temporary replacement for the ASIC, while the Raspberry Pi represents the system with which the chip will interact once fabricated. The tests demonstrated correct transmission and reception of characters through this interface, as well as the expected operation of the ring oscillator, verified through oscilloscope measurements. Additionally, a script was developed to automate the installation of Synopsys applications. This procedure was validated through the successful installation of Synopsys Installer and StarRC, significantly reducing the time and complexity required to prepare the working environment. The results obtained confirm the validity of the proposed methodology, the correct operation of the nanochip, and the usefulness of the automation tool developed.